1. Field of the Invention
This invention relates to a register bank circuit of for example, an operation processing device, and more particularly to a register bank circuit used in a microprocessor.
2. Description of the Related Art
As shown in FIG. 3, the register bank circuit includes a RAM (read/write memory) 21, a register pointer 22 for storing a register number, a bank pointer 23 for storing a bank number and an address generating circuit 24 for creating an address according to outputs of the bank pointer and register pointer. The register bank circuit uses the register bank system in which the address created in the address generating circuit 24 is supplied to the RAM 21 to permit the read or write operation with respect to a desired register.
However, the above register bank circuit has the following defects.
(a) Since the RAM 21 is used as a register, a period of time (access time) from when the address is supplied until data on a data bus 25 becomes effective is long. Therefore, when the register bank system is used in a microprocessor or the similar computer circuit, each time the read/write operation is performed, an access time delay is experienced. As a result, the processing speed of the microprocessor is limited, making it difficult to introduce the register bank system into a processor which requires high processing speed. PA1 (b) Since a RAM is used as a register, it is impossible to simultaneously access data stored in two different storage locations in the RAM. Therefore, if the register bank circuit is used in a microprocessor and when data of two registers is required to be processed, the processing speed becomes low in comparison with that of a system in which two registers can be simultaneously accessed since the two registers must be accessed one at a time. PA1 (a) Since the register is constructed by the register latch, the circuit scale becomes large in comparison with the system using the RAM of FIG. 3. For example, in a case where a circuit as shown in FIG. 5 is formed in an integrated configuration, an occupancy area which is more than twice the occupancy area required when the system using the RAM is utilized must be provided, and it becomes impossible to form a desired number of registers. PA1 (b) The number of control lines (the bank select signal lines and the register select signal lines) of the decoder 34 is large. Therefore, when it is formed in an integrated configuration, it requires a large area for the wiring in comparison with that required in the system using the RAM and the handling thereof becomes troublesome. PA1 (c) When the bank number is changed, it is necessary to redesign the decoder section. Since the scale of the decoder of this system is large, it is necessary to change the circuit on a large scale. This is a severe limitation when it is formed in an integrated configuration.
A register bank system as shown in FIG. 4 is proposed so as to eliminate the defects of the register bank circuit of FIG. 3.
The above system includes a plurality of register latch groups 31 respectively constituting banks, register pointers 32-1 and 32-2 for storing register numbers, a bank pointer 33 for storing a bank number and a decoder 34 for decoding outputs of the register pointers and the bank pointer. In this system, a maximum of two registers can be selected from a desired one of the banks among the plurality of register latch groups 31 in response to the output of the decoder. In this case, the number of register latch groups 31 correspond to the number of bank numbers.
Assume now that each bank is constituted by a register bank of 8-register construction which includes eight registers. FIGS. 5 and 6 show the detailed construction thereof. As shown in FIGS. 5 and 6, each register latch group 31 includes eight register latches R.sub.0 to R.sub.7. The output of the decoder 34 is constructed by 8 bank select signal sets (BS7 to BS0) and each bank select signal set is provided in one-to-one correspondence with the bank number and is connected to a corresponding one of the register latch groups 31. Further, since each register is selected by means of the register pointers 32-1 and 32-2, each bank select signal set is divided into two signal line groups (for example, BS7a and BS7b). Each signal line group includes eight control signal lines. The control signal lines are provided in one-to-one correspondence with the register numbers and respectively connected to the register latches R.sub.0 to R.sub.7. With this construction, one of the register latches R.sub.0 to R.sub.7 can be independently selected from each signal line group. The register latch selected by the first signal line group permits data to be subjected to the read/write operation via the data bus 35-1 and the register latch selected by the second signal line group permits data to be subjected to the read/write operation via the data bus 35-2.
A microprocessor having the above register bank circuit introduced therein can effect high-speed register transfer and the operation speed thereof can be enhanced.
However, the microprocessor has the following defects when compared with that having the register bank circuit as shown in FIG. 3.